The fabrication of various solid state devices requires the use of planar substrates, or semiconductor wafers, on which integrated circuits are fabricated. The final number, or yield, of functional integrated circuits on a wafer at the end of the IC fabrication process is of utmost importance to semiconductor manufacturers, and increasing the yield of circuits on the wafer is the main goal of semiconductor fabrication. After packaging, the circuits on the wafers are tested, wherein non-functional dies are marked using an inking process and the functional dies on the wafer are separated and sold. IC fabricators increase the yield of dies on a wafer by exploiting economies of scale. Over 1000 dies may be formed on a single wafer which measures from six to twelve inches in diameter.
Various processing steps are used to fabricate integrated circuits on a semiconductor wafer. These steps include sequential deposition of conductive and insulative layers on the silicon wafer substrate; formation of a photoresist or other mask such as titanium oxide or silicon oxide, in the form of the desired metal interconnection pattern, using standard lithographic or photolithographic techniques; subjecting the wafer substrate to a dry etching process to remove material from one or more conducting layers from the areas not covered by the mask, thereby etching the conducting layer or layers in the form of the masked pattern on the substrate; removing or stripping the mask layer from the substrate typically using reactive plasma and chlorine gas, thereby exposing the top surface of the conductive interconnect layer; and cooling and drying the wafer substrate by applying water and nitrogen gas to the wafer substrate.
The numerous processing steps outlined above are used to cumulatively apply multiple electrically conductive and insulative layers on the wafer and pattern the layers to form the circuits. Additional techniques, such as dual damascene processes, are used to form conductive vias which establish electrical contact between vertically-spaced conductive lines or layers in the circuits. The finished semiconductor product includes microelectronic devices including transistors, capacitors and resistors that form the integrated circuits on each of multiple die on a single wafer.
Transistors are important electrical elements in integrated circuits. Various design features, such as gate length and channel length, of transistors are being steadily increased to achieve higher package densities in the enhancement of device performance. In complex digital circuits such as microprocessors, fast-switching transistors are increasingly in demand. Thus, the channel or gate length, which is the distance between the drain region and the source region of a field effect transistor (FET), is being steadily reduced to reduce the electrical resistance of the transistor.
A cross-section of a typical transistor structure 10 is shown in FIG. 1. The transistor structure 10 is fabricated between spaced-apart shallow trench isolation (STI) regions 24 (one of which is shown in FIG. 1), typically silicon dioxide, which are initially formed in a silicon wafer substrate 12. An insulating layer 26, such as silicon dioxide, covers the surface of the substrate 12. The transistor structure 10 includes an electrically-insulating gate oxide layer 14, which is typically a thermally-grown silicon dioxide and is formed over the substrate 12, between the STI regions 24. A gate electrode 16, which is typically polysilicon, is formed on the gate oxide layer 14. A TEOS or other oxide layer 18 and a nitride layer 20 are sequentially formed on respective sides of the gate electrode 16.
After anisotropic etching of the nitride layer 20, the oxide layer 18 and the nitride layer 20 together form an electrically-insulating sidewall spacer, also known as a mini-spacer 22. Relative to the gate electrode 16, the upper surfaces of the oxide layer 18 and nitride layer 20 are characterized by a top loss 28, which corresponds to material lost during etching. The traditional sidewall spacer 22, shown in FIG. 1, extends in generally perpendicular relationship to the plane of the substrate 12. In some applications, the sidewall spacer 22 is tilted with respect to the plane of the substrate 12 and is known as an offset spacer.
Ion implantation is used to form active regions on the transistor structure 10. The ion implantation process includes the implantation of dopant ions in the substrate 12 to form a source/drain implant in the source and drain regions. Because the sidewall spacers 22 define the boundaries of the source/drain implant regions in the substrate 12, the width and top loss 28 of the sidewall spacers 22 after etching are important to achieve proper ion implantation in the substrate 12.
As microelectronic fabrication integration levels have increased and patterned microelectronic conductor layer dimensions have decreased, it has become increasingly important within the art of microelectronic fabrication to form within microelectronic fabrications patterned microelectronic conductor layers, such as but not limited to gate electrodes within field effect transistors (FETs), as well as patterned microelectronic conductor interconnect layers, with a uniform sidewall profile. Uniform sidewall profiles are particularly desirable within gate electrodes in field effect transistors since gate electrode linewidth and profile define operational parameters of the integrated circuit within which is formed the FET. Furthermore, the width of sidewall spacers has decreased with the increased miniaturization of device features.
Throughout the course of semiconductor fabrication, it is frequently necessary to measure various parameters of the sidewall spacers in a transistor structure, such as, for example, the spacer width and top loss after etching. Conventional methods for measuring the width of the sidewall spacers includes in-line CD SEM (scanning electron micrograph), in the case of traditional spacers, and TEM (transmission electron microscopy), in the case of offset spacers. Conventional methods for measuring the spacer top loss include off-line SEM (for traditional spacers) and TEM (for thin offset spacers).
The conventional SEM and TEM methods for measuring the spacer width and spacer top loss have several drawbacks. Due to image contrast issues and line edge roughness issues, it is often difficult to obtain reliable results using in-line SEM. Furthermore, on offset spacers, the sidewalls are often too thin for accurate spacer width measurement using SEM, so TEM must be used. TEM, however, is a time-consuming process and cannot be used in routine in-line measurement. Accordingly, a new and improved method is needed to measure the spacer width and top loss of sidewall spacers in semiconductor fabrication.
An object of the present invention is to provide a novel method for measuring spacer profiles in semiconductor fabrication.
Another object of the present invention is to provide a novel method which uses optical scatterometry to measure various aspects of sidewall spacers in semiconductor fabrication.
Yet another object of the present invention is to provide an optical scatterometry method of sidewall spacer analysis which includes providing a grating bar having multiple grating targets that simulate the CD (critical dimension), height, spacer width, top loss and other physical characteristics or the physical geometry of a spacer on a semiconductor wafer; generating theoretical optical scatterometry spectra of the grating targets on the grating bar; generating an experimental optical scatterometry spectrum of spacers fabricated on a production wafer; and comparing the theoretical optical scatterometry spectra obtained from the grating targets with the experimental optical scatterometry spectrum obtained from the spacers to determine a match which indicates the spacer width, top loss or other structural characteristics or the structural geometry of the spacers.
Still another object of the present invention is to provide an optical scatterometry method of spacer analysis which is efficient, can be used in-line and does not require destruction of a sample to determine various structural characteristics of spacers.